This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-218364, filed Aug. 2, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a suppresser which comprises MOS transistors, and more particularly to a suppresser fit for use in processing video signals in television receivers.
Hitherto, gamma correction has been widely performed to compress the white-level side component of a video signal in television receivers. In the image-receiving tube of a television receiver, the input drive voltage and the output electron-beam current generally have no linear input-output relation. Rather, the input drive voltage and the input electron-beam current has an exponential input-output relation, i.e., a non-linear input-output relation. Therefore, there exits the trend that the white-level side component of the video signal is amplified more than the black-side level component of the video signal. To compensate for the non-linear input-output relation, gamma correction is usually performed, suppressing the white-side level component of the video signal before the video signal is supplied to the image-receiving tube.
A suppresser is used to accomplish gamma correction. Most suppressers for use in the gamma correction comprise bipolar transistors, as disclosed in, for example, Jpn. Pat. Appln. KOKAI Publication No. 6-261228. FIG. 9 is a schematic diagram of a suppresser that comprises a bipolar transistor. FIG. 10 represents the input-output voltage characteristic of the suppresser.
The suppresser shown in FIG. 9 comprises an input terminal 21, an output terminal 22, a bias-potential input terminal 23, a PNP-type bipolar transistor 24, a buffer circuit 25 of voltage follower type, a resistor 27, and a resistor 28. The buffer circuit 25 has its input connected to the input terminal 21 and its output connected to the output terminal 22 by the resistor 27. The resistor 28 and the PNP-type bipolar transistor 24 are connected in series between the output terminal 22 and the ground potential Vss. The base of the bipolar transistor 24 is connected to the input terminal 23 of the bias potential Vb. The buffer circuit 25 converts the image signal input to the input terminal 21 into an impedance, which is applied to the output terminal 22 through the resistor 27.
In the suppresser, the bipolar transistor 24 is not conducting while the input signal remains at level Vin that is equal to or lower than the sum (Vb+VBE) of the bias potential Vb and the base-emitter voltage VBE of the bipolar transistor 24. Hence, the input signal has attains a gain of 0 dB. In other words, the signal is output from the terminal 22, neither amplified nor suppressed. When the level Vin of the input signal rises above Vb+VBE, the bipolar transistor 24 is turned on. The level Vout of the output signal is therefore suppressed as indicated by the solid line A shown in FIG. 10. The suppression level r is given as: R1/(Re+R1+R2), where R1 is the resistance of the resistor 27, R2 is the resistance of the resistor 28, and Re is the output impedance of the bipolar transistor 24. The solid line A shown in FIG. 10 bends at Vb+VBE, showing that the gain of the output signal is greater when the level Vin of the input signal lower than Vb+VBE than when the level Vin is higher than Vb+VBE. Actually, however, the gain gradually changes due to the output impedance of the bipolar transistor 24. Thus, the ratio of the output-signal level Vout of the input-signal level Vin changes as indicated by the broken curve B shown in FIG. 10, but not so much as indicated by the solid bending line A.
Recently, an attempt has been made everywhere to use MOS transistors in analog signal-processing circuits, not using bipolar transistors as has been practiced hitherto, in order lower the manufacturing cost of the analog signal-processing circuits. In this technological trend it is desired that suppressers be developed which comprise MOS transistors. The suppresser of FIG. 9, however, cannot have desired characteristics, merely by replacing the bipolar transistor 24 with a MOS transistor.
This is because MOS transistors have an output impedance much higher than that of bipolar transistors. Generally, the output impedance of a transistor differs from the design value due to errors in the manufacturing process and changes in the temperature of the transistor.
In the suppresser shown in FIG. 9, the output impedance Re of the bipolar transistor 24 is negligibly small, far less than the resistances R1 and R2 of resistors 27 and 28, which determine the suppression level r the circuit achieves. Thus, the suppression level r depends on almost only the resistances R1 and R2. An error, if any, in the output impedance Re of the bipolar transistor 24 does not influence the suppression level r so much.
By contrast, a MOS transistor has an output impedance Re which is comparable to the resistance R1 of the resistor 27 and the resistance R2 of the resistor 28. If the bipolar 24 is replaced by a MOS transistor, the output impedance Re of the MOS transistor will greatly influence the suppression level r the suppresser achieves. Consequently, the suppression level r will much change if the output impedance Re of the MOS transistor differs from the design value due to errors resulting from the manufacturing process variation or errors resulting from the temperature variation. The suppresser fails to have stable operating characteristics. Furthermore, since the MOS transistor has a much higher output impedance than the bipolar transistor 24, the ratio of the output-signal level Vout of the input-signal level Vin changes less as indicated by the one-dot dashed curve C in FIG. 10, than in the case where the bipolar transistor 24 is used. Inevitably, the operating characteristic of the suppresser cannot be sufficiently.
As mentioned above, it has been increasingly expected in recent years that analog signal-processing circuits be developed which comprising MOS transistors. However, a suppresser comprising a MOS transistor can hardly have stable operating characteristics because the MOS transistor has a high output impedance.
The present invention has been made in consideration of the foregoing. The object of the invention is to provide a suppresser which comprises MOS transistors and which can yet exhibit stable operating characteristics, despite the fact that the output impedance of each MOS transistor differs from the design value due to errors in the manufacturing process and changes as the temperature of the transistor varies.
To attain the object, a suppresser circuit according to a first aspect of the present invention, comprises a first voltage-to-current converting circuit configured to convert an input voltage signal to an output current signal; a second voltage-to-current converting circuit having a non-inverting input terminal for receiving a predetermined bias potential and an inverting input terminal for receiving the input voltage signal; and a current-limiting element connected between the first and second voltage-to-current converting circuits, configured to substantially stop a flow of current between the first and second voltage-to-current converting circuits while the input voltage signal remains at a level equal to or lower than the bias potential, and decrease the output current of the first voltage-to-current converting circuit while the input voltage signal remains at a level higher than the bias potential.
In the suppresser circuit according to the first aspect of the present invention, the first voltage-to-current converting circuit may have a non-inverting input terminal supplied with the input voltage signal and an inverting input terminal connected to an output terminal.
In the suppresser circuit according to the first aspect of the present invention, the current-limiting element may comprise a PN-junction diode connected between the first and second voltage-to-current converting circuits.
In the suppresser circuit according to the first aspect of the present invention, the second voltage-to-current converting circuit may have transconductance smaller than that of the first voltage-to-current converting circuit.
In the suppresser circuit according to the first aspect of the present invention, the suppresser circuit may further comprise at least one additional voltage-to-current converting circuit having a non-inverting input terminal and an inverting input terminal and at least one additional current-limiting element, and in which a pair of the second voltage-to-current converting circuit and the current-limiting element, and a pair of the additional voltage-to-current converting circuit and the additional current-limiting element are connected in parallel to the first voltage-to-current converting circuit, and different bias potentials are applied to the non-inverting input terminals of the second voltage-to-current converting circuit and the additional voltage-to-current converting circuit.
A suppresser circuit according to a second aspect of the present invention, comprises an input terminal; an output terminal; a first potential-applied node; a second potential-applied node; a first differential circuit composed of first and second MOS transistors of a first conductivity type, the first MOS transistor having a gate connected to the input terminal, a source and a drain, and the second MOS transistor having a gate and a drain, both connected to the output terminal, and a source; a first current source connected at one end to the sources of the first and second MOS transistors and at the other end to the first potential-applied node; a first current mirror circuit composed of third and fourth MOS transistors of a second conductivity type, the third MOS transistor having a gate and a drain, both connected to the drain of the first MOS transistor, and a source connected to the second potential-applied node, and the fourth MOS transistor having a gate connected to the gate of the third MOS transistor, a drain connected to the drain of the second MOS transistor and a source connected to the second potential-applied node; a second differential circuit composed of fifth and sixth MOS transistors of the first conductivity type, the fifth MOS transistor having a source, a drain and a gate for receiving a predetermined bias potential, and the sixth MOS transistor having a source, a drain and a gate connected to the input terminal; a second current source connected at one end to the sources of the fifth and sixth MOS transistors and at the other end to the first potential-applied node; a second current mirror circuit composed of seventh and eighth MOS transistors of the second conductivity type, the seventh MOS transistor having a gate and a drain, both connected to the drain of the fifth MOS transistor, and a source connected to the second potential-applied node, and the eighth MOS transistor having a gate connected to the gate of the seventh MOS transistor, a drain connected to the drain of the sixth MOS transistor and a source connected to the second potential-applied node; and a third current mirror circuit composed of ninth and tenth MOS transistors of the second conductivity type, the ninth MOS transistor having a gate and a drain, both connected to the drain of the eighth MOS transistor, and a source connected to the second potential-applied node, and the tenth MOS transistor having a gate connected to the gate of the ninth MOS transistor, a drain connected to the drain of the third MOS transistor and a source connected to the second potential-applied node.
In the suppresser circuit according to the second aspect of the present invention, the first and second MOS transistors may have a channel width-to-length ratio W/L, and the fifth and sixth MOS transistors may have a channel width-to-length ratio W/L different from that of the first and second MOS transistors.
In the suppresser circuit according to the second aspect of the present invention, the first and second current sources may supply currents of different values.
In the suppresser circuit according to the second aspect of the present invention, the ninth and tenth MOS transistors may have different channel width-to-length ratios W/L.
In the suppresser circuit according to the second aspect of the present invention, the suppresser circuit may further comprise a third differential circuit composed of eleventh and twelfth MOS transistors of the first conductivity type, the eleventh MOS transistor having a source, a drain and a gate for receiving a bias potential different to the bias potential applied to the gate of the fifth MOS transistor, and the twelfth MOS transistor having a source, a drain and a gate connected to the input terminal; a third current source connected at one end to the sources of the eleventh and twelfth MOS transistors, and at the other end to the first potential-applied node; a fourth current mirror circuit composed of thirteenth and fourteenth MOS transistors of the second conductivity type, the thirteenth MOS transistor having a gate and a drain, both connected to the drain of the eleventh MOS transistor, and a source connected to the second potential-applied node, and the fourteenth MOS transistor having a gate connected to the gate of the thirteenth MOS transistor, a drain connected to the drain of the twelfth MOS transistor and a source connected to the second potential-applied node; and a fifth current mirror circuit composed of fifteenth and sixteenth MOS transistors of the second conductivity type, the fifteenth MOS transistor having a gate and a drain, both connected to the drain of the fourteenth MOS transistor, and a source connected to the second potential-applied node, and the sixteenth MOS transistor having a gate connected to the gate of the fifteenth MOS transistor, a drain connected to the drain of the third MOS transistor and a source connected to the second potential-applied node.
A video signal processing circuit according to a third aspect of the present invention, comprises a first signal processing circuit configured to receive a chromatic signal of a video signal, and process the chromatic signal to generate a color-difference signal; a second signal processing circuit configured to receive a luminance signal of the video signal, and process the luminance signal to suppress a white-level component thereof; and a metric circuit configured to receive output signals of the first and second signal processing circuits, and compose thereof, the second signal processing circuit including a first voltage-to-current converting circuit configured to convert an input voltage signal to an output current signal; a second voltage-to-current converting circuit having a non-inverting input terminal for receiving a predetermined bias potential and an inverting input terminal for receiving the input voltage signal; and a current-limiting element connected between the first and second voltage-to-current converting circuits, configured to substantially stop a flow of current between the first and second voltage-to-current converting circuits while the input voltage signal remains at a level equal to or lower than the bias potential, and decrease the output current of the first voltage-to-current converting circuit while the input voltage signal remains at a level higher than the bias potential.
In the suppresser circuit according to the third aspect of the present invention, the first voltage-to-current converting circuit may have a non-inverting input terminal supplied with the input voltage signal and an inverting input terminal connected to an output terminal.
In the suppresser circuit according to the third aspect of the present invention, the current-limiting element may comprise a PN-junction diode connected between the first and second voltage-to-current converting circuits.
In the suppresser circuit according to the third aspect of the present invention, the second voltage-to-current converting circuit may have transconductance smaller than that of the first voltage-to-current converting circuit.
In the suppresser circuit according to the third aspect of the present invention, the suppresser circuit may further comprise at least one additional voltage-to-current converting circuit having a non-inverting input terminal and an inverting input terminal and at least one additional current-limiting element, and in which a pair of the second voltage-to-current converting circuit and the current-limiting element, and a pair of the additional voltage-to-current converting circuit and the additional current-limiting element are connected in parallel to the first voltage-to-current converting circuit, and different bias potentials are applied to the non-inverting input terminals of the second voltage-to-current converting circuit and the additional voltage-to-current converting circuit.
In the suppresser circuit according to the third aspect of the present invention, the first voltage-to-current converting circuit may include a first differential circuit composed of first and second MOS transistors of a first conductivity type, the first MOS transistor having a gate connected to an input terminal, a source and a drain, and the second MOS transistor having a gate and a drain, both connected to an output terminal, and a source; a first current source connected at one end to the sources of the first and second MOS transistors and at the other end to a first potential-applied node; and a first current mirror circuit composed of third and fourth MOS transistors of a second conductivity type, the third MOS transistor having a gate and a drain, both connected to the drain of the first MOS transistor, and a source connected to a second potential-applied node, and the fourth MOS transistor having a gate connected to the gate of the third MOS transistor, a drain connected to the drain of the second MOS transistor and a source connected to the second potential-applied node, the second voltage-to-current converting circuit may include a second differential circuit composed of fifth and sixth MOS transistors of the first conductivity type, the fifth MOS transistor having a source, a drain and a gate for receiving a predetermined bias potential, and the sixth MOS transistor having a source, a drain and a gate connected to the input terminal; a second current source connected at one end to the sources of the fifth and sixth MOS transistors and at the other end to the first potential-applied node; and a second current mirror circuit composed of seventh and eighth MOS transistors of the second conductivity type, the seventh MOS transistor having a gate and a drain, both connected to the drain of the fifth MOS transistor, and a source connected to the second potential-applied node, and the eighth MOS transistor having a gate connected to the gate of the seventh MOS transistor, a drain connected to the drain of the sixth MOS transistor and a source connected to the second potential-applied node, and the current-limiting element may include a third current mirror circuit composed of ninth and tenth MOS transistors of the second conductivity type, the ninth MOS transistor having a gate and a drain, both connected to the drain of the eighth MOS transistor, and a source connected to the second potential-applied node, and the tenth MOS transistor having a gate connected to the gate of the ninth MOS transistor, a drain connected to the drain of the third MOS transistor and a source connected to the second potential-applied node. The first and second MOS transistors may have a channel width-to-length ratio W/L, and the fifth and sixth MOS transistors may have a channel width-to-length ratio W/L different from that of the first and second MOS transistors. The first and second current sources may supply currents of different values. The ninth and tenth MOS transistors may have different channel width-to-length ratios W/L. The suppresser circuit may further comprise a third differential circuit composed of eleventh and twelfth MOS transistors of the first conductivity type, the eleventh MOS transistor having a source, a drain and a gate for receiving a bias potential different than the bias potential applied to the gate of the fifth MOS transistor, and the twelfth MOS transistor having a source, a drain and a gate connected to the input terminal; a third current source connected at one end to the sources of the eleventh and twelfth MOS transistors, and at the other end to the first potential-applied node; a fourth current mirror circuit composed of thirteenth and fourteenth MOS transistors of the second conductivity type, the thirteenth MOS transistor having a gate and a drain, both connected to the drain of the eleventh MOS transistor, and a source connected to the second potential-applied node, and the fourteenth MOS transistor having a gate connected to the gate of the thirteenth MOS transistor, a drain connected to the drain of the twelfth MOS transistor and a source connected to the second potential-applied node; and a fifth current mirror circuit composed of fifteenth and sixteenth MOS transistors of the second conductivity type, the fifteenth MOS transistor having a gate and a drain, both connected to the drain of the fourteenth MOS transistor, and a source connected to the second potential-applied node, and the sixteenth MOS transistor having a gate connected to the gate of the fifteenth MOS transistor, a drain connected to the drain of the third MOS transistor and a source connected to the second potential-applied node.
The suppression level of the suppresser circuit is determined from the ratio between the transconductance of the first voltage-to-current converting circuit composed of the first differential circuit, first current source and first current mirror circuit and the transconductance of the second voltage-to-current converting circuit composed of the second differential circuit, second current source and first current mirror circuit. Therefore, the first and second voltage-to-current converting circuits cooperate to compensate for the changes in the characteristics of the suppresser circuit, which result from the temperature changes of each transistor and the deviation of the output impedance of each MOS transistor form its design value, due to errors in the manufacturing process.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.